However, and this is very perplexing, there is no additional information related to the "separate application note." My suspicion is that Sensirion intended to include a link to this app note but then simply forgot to include it; perhaps additional information will be provided in the datasheet next revision.
The decoupling capacitors (C4, C5, C6, C7, C9, C10, C11) are arranged around the perimeter of the chip, very close to their respective power pins and to the vias that connect the caps to the internal planes. Notice how the smaller cap is always closer to the power pin; this is because we rely more on the lower-value capacitor for high-frequency bypassing, and thus the first priority is minimizing the inductance and resistance between the smaller cap and the pin.
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