It’s always good to be cognizant of trace lengths when you’re laying out a parallel bus, though at moderate frequencies it is nothing to stress about. The propagation time for a signal traveling through a trace is maybe 150 picoseconds/inch. So if you have two traces with a length mismatch of one inch, one signal will arrive 150 ps after the other signal. If your signals are transitioning at a frequency whose corresponding period is much greater than 150 ps, this one-inch mismatch won’t cause problems. Even at 100 MHz (which is pretty fast for a parallel bus), the period is 10 ns, i.e., ~67 times larger than the time-of-arrival discrepancy for a one-inch mismatch.
The decoupling capacitors (C4, C5, C6, C7, C9, C10, C11) are arranged around the perimeter of the chip, very close to their respective power pins and to the vias that connect the caps to the internal planes. Notice how the smaller cap is always closer to the power pin; this is because we rely more on the lower-value capacitor for high-frequency bypassing, and thus the first priority is minimizing the inductance and resistance between the smaller cap and the pin.
Nolanwebdev - Wiring Diagram Images Collection
Copyright © 2003 - 2018 Domain Media. All sponsored products, company names, brand names, trademarks and logos arethe property of their respective owners.